Phase 5 • Direct Leader QUIC / TPU Execution Lab

Real-Time Benchmarking

Empirical 2x2 Factorial evaluation of Control vs Celor-Aware consensus timing across JSON-RPC and Direct Leader QUIC (TPU) transports.

Latency Domain Separation • Scientific Metric Classification

Strict invariant: Internal execution, provider transport lag, and protocol consensus finality are distinct physical phenomena.

AGENTS.MD BENCHMARKING RULE #1
1. Celor Processing[MEASURED CLOCK]
0.67µs – 2.0µs
Monotonic in-memory ring buffer normalization & state insert. NOT consensus finality.
2. Execution Latency[UNCHANGED]
~400ms slot window
SVM program bytecode execution & compute unit accounting remain 100% identical.
3. Provider / Obs Lag[TRANSPORT DELAY]
16ms obs / 1,200ms ws lag
Upstream RPC WebSocket subscription broadcast delay. NOT consensus finality.
4. Live Consensus Finality[VOTOR BLS]
~231ms observed
Alpenglow Votor BLS certificate fast path on Devnet (Genesis #504,148,999) vs 150ms target / 12.8s TowerBFT.
Confirmed Rate
—
Ctrl: —•Δ 0%
End-to-end inclusion
Confirm Latency (p50)
—
Ctrl: —•Δ 0ms
Monotonic hardware clock
Landing Slot Delta
+—
Ctrl: +— slots
Median slots to inclusion
Stale BH / Handoff Miss
0 / 0
Ctrl: 0 / 0
Avoided via freshness state

Phase 7 Master Baseline • Empirically Recorded Benchmarks

Monotonic hardware clock timings recorded across N = 10,000 iterations under release profiling. Zero simulated metrics.

STRICTLY [MEASURED]
End-to-End Pipeline (p50)2.00µsZero heap allocation in hot path
End-to-End Pipeline (p99)8.58µsTail latency bound under load
Drop & Failure Rate0.00%10,000 / 10,000 events processed
PIPELINE STAGEP50P90P95P99MAXPROVENANCE
Stage 1: Raw Stream -> Normalized Event166ns250ns291ns375ns1250ns[MEASURED]
Stage 2: Normalized Event -> BankGraph Insert708ns1750ns2083ns3292ns6417ns[MEASURED]
Stage 3: BankGraph -> Canonical Resolution750ns875ns959ns2875ns5667ns[MEASURED]
Stage 4: Canonical -> Finality Registration250ns333ns375ns792ns2167ns[MEASURED]
TOTAL: End-to-End Consensus Pipeline2,000ns (2.0µs)3,208ns (3.2µs)3,834ns (3.8µs)8,583ns (8.6µs)15,501ns[MEASURED]
Clock source: monotonic hardware clock (Instant::now)Rule: Simulated benchmarks can NEVER be cited as evidence of real-world speed